Read Access:
When the PC sends data to the FPGA over
USB, the device will assert the Receive Full status pin (RXF#) to
let the FPGA know that data is available. The FPGA then reads the
data until the receiver full status bit goes inactive, indicating
no more data is available to read.
Signal Description:
D[7..0]: Bi-directional data bus.
RXF#: When high, do not read data from the FIFO. When low,
there is data available in the FIFO which can be read by strobing
RD# low then high again.
RD#:
Enables current FIFO data byte on D[7..0] when low. Fetches the
next FIFO data byte (if available) from the receive FIFO buffer
when RD# goes from low to high.
Write Access:
To send data from the FPGA
to the host PC simply write the byte wide data into the device
when the Transmitter Empty status pin (TXE#) is active. If the
transmit buffer fills up, the device de-asserts TXE# in order to
stop further data being written to the device until some of the
FIFO data has been transferred over the USB.
Signal Description:
D[7..0]: Bi-directional data bus.
TXE#: When high, do not write data into the FIFO. When low,
data can be written into the FIFO by strobing WR high then low.
WR: Writes the data byte on the D[7..0] into the transmit
FIFO buffer when WR goes from high to low.
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